Array substrate for liquid crystal display device and the fabrication method of the same

ABSTRACT

The present invention discloses an array substrate for an active-matrix LCD device and a method of fabricating the same. The array substrate reduces the number of masks used in the fabrication process so that reliability is enhanced and the cost is reduced over the conventional device and method.

CROSS REFERENCE

This application claims the benefit of Korean Patent Application No. 1999-0046346, filed on Oct. 25, 1999, under 35 U.S.C. §119, the entirety of which is hereby incorporated by reference.

BACKGROUND OF THE INVENTION

The present invention relates to an active-matrix liquid crystal display (LCD) device and a method of fabricating the same, and more particularly, to an array substrate having thin film transistors for the active-matrix LCD device and the method of fabricating the array substrate.

An active matrix type LCD device, employing a thin film transistor (TFT) as a switching device, is typically made up of two array substrates with a liquid crystal material interposed therebetween. One substrate, which is the array substrate, has a matrix array of TFTs and pixel electrodes. The opposing substrate, which is the color filter substrate, includes a light-shielding film (also known as the black matrix), a color filter, and a common electrode.

For the array substrate, an inverted staggered type TFT is widely employed because of its simple structure and superior quality. The inverted staggered type TFT is further divided into a back-channel-etch type and an etching-stopper type, which are differentiated according to the methods of forming a channel in the TFT. Between the two, the back-channel-etch type has a simpler structure.

A typical array substrate manufacturing process requires repeated steps of depositing and patterning various layers. The patterning steps involve photolithography masks. Each photolithography step is facilitated using one mask, and the number of masks used in the fabrication process is a critical factor in determining the number of patterning steps. Namely, the production cost depends heavily on the number of masks used in the manufacturing process.

Referring to the attached drawings, a back-channel-etching type structure of an array substrate of an LCD device manufactured by a conventional method will be explained in detail.

As shown in FIG. 1, the LCD device 20 includes an array substrate 2, a color filter substrate 4 opposing the array substrate 2, a liquid crystal 10 interposed between, and a sealant 6 formed at the periphery of the gap between the two substrates 2 and 4. The sealant 6 prevents the liquid crystal 10 from leaking out of the LCD device 20.

The array substrate 2 includes a substrate 1, a TFT 5, and a pixel electrode 14. The TFT 5 acts as a switching element for changing the orientation of the liquid crystal 10, and the pixel electrode 14 is used as a first electrode to apply electric field to the liquid crystal 10.

The color filter substrate 4 includes a substrate 11, a color filter 8, and a common electrode 12. The color filter 8 is used for displaying colors and the common electrode 12 is used as a second electrode to apply an electric field to the liquid crystal 10.

Referring to FIG. 2, a detailed description of the structure and operation of the array substrate 2 will be provided.

On the substrate 1 of the array substrate 2, a gate line 22 is horizontally formed and a data line 24 is formed perpendicular thereto. The pixel electrode 14 is formed within the rectangular area defined by the gate and data lines 22 and 24. Near the crossing point between the gate and data lines 22 and 24, a portion of the gate line 22 is used as a gate electrode 26. Also, at one end of the gate line 22, a gate pad 18 is positioned and the gate pad contact hole 21 is formed in the gate pad 18.

Further, again near the crossing point, the data line 24 is extended to form a source electrode 28, and a drain electrode 30 is formed spaced apart from the source electrode 28. Also at one end of the data line 24, a data pad 20 is positioned and the data pad contact hole is formed in the data pad 23.

Spaced apart from the drain electrode 30 and over a portion of the gate line 22, an island-shaped capacitor electrode 32 is formed from the same layer as the data line 24. An extended portion of the pixel electrode 14 overlaps the capacitor electrode 32, and together with the extended portion forms a storage capacitor 7 to store electric charges.

A capacitor contact hole 36 is formed above the capacitor electrode 32 to electrically connect the pixel electrode 14 with the capacitor electrode 32. Another portion of the pixel electrode 14 also overlaps a portion of the drain electrode 30, and a drain contact hole 34 is formed at the overlapped portion to electrically connect the drain electrode 30 and the pixel electrode 14.

As explained previously, the TFT 5, which includes the gate, source, and drain electrodes 26, 28 and 30, functions as a switch for applying an electric field to the liquid crystal 10 (shown in FIG. 1). That is to say, in operation, if a signal is applied to the gate electrode 26 of the TFT 5, an electrical connection is established between the data line 24 and the pixel electrode 14. When the gate electrode 26 is turned on, electric field is applied to the pixel electrode 14 according to the signal, from an external circuit (not shown), applied to the data line 24 via the data pad 20.

Next, referring to FIGS. 3A to 7A and 3B to 7B, a more detailed description of the structure and the fabrication method of the TFT and the storage capacitor will be provided. FIGS. 3A to 7A illustrate sequential fabrication steps of a cross-section take along a line “IIIa—IIIa” of FIG. 2, and FIGS. 3B to 7B illustrate corresponding sequential fabrication steps of a cross-section taken along a line “IIIb—IIIb” of FIG. 2.

As shown in FIGS. 3A and 3B, a first metallic material is deposited on a surface of the substrate 1 and patterned with a first mask to form the gate line 22 including the gate electrode 26 and gate pad 18 (shown in FIG. 2). For the first metallic material, a highly conductive metal such as aluminum (Al), aluminum alloy, or molybdenum (Mo) is preferred.

As shown in FIGS. 4A and 4B, a first insulating material is then deposited to form a gate insulating layer 50. On the gate insulating layer 50, a semiconductor material is deposited and doped with impurities and patterned with a second mask to form a semiconductor layer 52 and an ohmic contact layer 54, thereby defining a first intermediate structure.

Then, as shown in FIGS. 5A and 5B, a second metallic material is deposited over the first intermediate structure and patterned with a third mask to form the source and drain electrodes 28 and 30 and the data line 24. The data line 24 is connected with the source electrode 28 (FIG. 5A). At the same time, over a portion of the gate line 22, the second metallic material is used to form the capacitor electrode 32 with the third mask (FIG. 5B).

Afterwards, a portion of the ohmic contact layer 54 is also etched away to form a back channel 56 (FIG. 5A). At this point a second intermediate structure is defined, including the TFT 5 that is made up of the gate, source, and drain electrodes 26, 28, and 30, the semiconductor layer 52, the ohmic contact layer 54, and the back channel 56.

As shown in FIGS. 6A and 6B, over the second intermediate structure, a second insulating material is deposited and patterned with a fourth mask to form a passivation layer 58. The passivation layer 58, protecting the TFT 5 and the capacitor electrode 32, is preferably selected from inorganic-based silicon nitride (SiN_(x)), silicon oxide (SiO₂), or organic-based benzocyclobutene (BCB) because they exhibit high light-transmissivity, a moisture-proof quality, and high durability. By patterning the second insulating layer with the fourth mask, the data pad contact, the drain contact, and the capacitor contact holes 23, 34 and 36 are formed, thereby defining a third intermediate structure.

Then as shown in FIGS. 7A and 7B, on the third intermediate structure, a transparent conductive material is deposited and patterned with a fifth mask to form the pixel electrode 14. The pixel electrode 14 is electrically connected with the drain electrode 30 and the capacitor electrode 32 via the drain and capacitor contact holes 34 and 36, respectively. The transparent conductive material is preferably made of indium tin oxide (ITO).

FIG. 8 shows the above-described fabricating process in a block diagram.

In step ST200, the substrate is cleaned to be free from contaminants on the surface.

In step ST210, the gate line 22, gate electrode 26, and gate pad 18 are formed by depositing the first metallic material and patterning the first metal layer by using the first mask.

In step ST220, the gate insulating layer 50 is formed by depositing the first insulating layer and patterned using the second mask. Then the semiconductor and ohmic contact layers 52 and 54, respectively, are formed by sequentially depositing the semiconductor materials and doped semiconductor materials and patterning the materials.

In step ST230, the source and drain electrodes 28 and 30, the data line 24, and the capacitor electrode 32 are formed by depositing and patterning the second metallic layer using a third mask.

In step ST240, the back channel 56 is formed by etching the ohmic contact layer 54 using the source and drain electrodes as a mask.

In step ST250, the passivation layer 58 and the data, drain, and the capacitor contact holes (23, 34, and 36 respectively) are formed by depositing and patterning the second insulating layer using a fourth mask.

In step ST260, the pixel electrode 14 is formed by depositing and patterning the transparent conductive material using a fifth mask.

The above-described conventional method of fabricating the array substrate of the LCD device employs five masks. If aluminum is used to form the gate electrode, at least two additional masks are needed to prevent hillocks, i.e., so that gate line defects can be avoided. Accordingly, at least five masking steps, and as many as seven steps, are required in the conventional fabricating process of the array substrate.

As mentioned above, a decrease in masking steps would decrease the manufacturing cost and improve the manufacturing yield.

SUMMARY OF THE INVENTION

In view of the foregoing and other problems of the conventional manufacturing method of the LCD device, it is an object of the present invention to provide a relatively low cost manufacturing method of the array substrate for the LCD device.

To achieve the above-mentioned objects, the present invention provides a method of manufacturing an array substrate of a LCD device and an array substrate fabricated by the method. The method includes preparing a substrate; forming a plurality of gate lines, a plurality of gate pads and gate pad contact holes, and a first insulating layer by depositing a first metal layer and a first insulating layer sequentially on a surface of the substrate and patterning the first metal layer and the first insulating layer with a first mask such that the plurality of gate lines are parallel with and spaced apart from each other wherein each gate pad is positioned at one end of a corresponding gate line, and wherein each gate pad contact hole has a shape of a through hole passing through the gate pad and the first insulating layer; forming a second insulating layer, a semiconductor layer, an ohmic contact layer, and a second metal layer by depositing a second insulating material, a semiconductor material, a doped semiconductor layer, and a second metallic material sequentially over the surface of the substrate; forming a plurality of data lines, data pads, source electrodes, drain electrodes, and drain contact holes by patterning the second metal layer with a second mask wherein the data lines cross the gate lines, each data pad is positioned at one end of a corresponding data line, each source electrode is extended from the data lines near the crossing point of the gate line and the data line, the drain electrode is spaced apart from the source electrode, and wherein the drain contact hole is positioned on the drain electrode; forming a plurality of back-channels by etching away portions of the ohmic contact layer using the patterned second metal layer as a mask, wherein the channel is positioned between the source and the drain electrodes; depositing a third insulating layer on the data lines, the source and the drain electrodes, and the data pads; patterning the third insulating layer, the ohmic contact layer, the semiconductor layer and second insulating layer with a third mask to form a passivation layer, wherein the passivation layer has a data pad contact hole having a shape of a through hole positioned over the data pad, and wherein the passivation layer covers the patterned second metal layer and a peripheral portion of the gate line; and forming a plurality of pixel electrodes, data pad electrodes, and gate pad electrodes by depositing a transparent conductive layer on the passivation layer, and patterning the transparent conductive layer by a fourth mask, wherein a portion of the pixel electrode overlaps the peripheral portion of the gate line, the pixel electrode is electrically connected with the drain electrode via the drain contact hole, the data pad electrode is electrically connected with the data pad by way of the data pad contact hole, and wherein the gate pad electrode is electrically connected with the gate pad via the gate pad contact hole.

Another method includes steps of depositing a first conducting material and a first insulating material on top of the first conducting material on a substrate; using a first mask, forming a gate line, a gate pad at one end the gate line, a first insulating layer over the gate line and gate pad, and at least one gate pad contact hole the gate pad; depositing, in sequence, a second insulating layer, a semiconductor layer, an ohmic contact layer, and a second conducting material over the resulting structure; using a second mask to pattern the second conducting material, forming a data line such that the data line cross the gate line and forming source and drain electrodes the crossing point; forming a back channel between the source and drain electrodes by etching the ohmic contact layer using the source and drain electrodes as a mask; forming a passivation layer by depositing a third insulating layer over the resulting structure; using a third mask, removing the second insulating layer, the semiconductor layer, the ohmic contact layer, and the passivation layer over a portion of the gate line and the gate pad; depositing a transparent conductive material over the resulting structure; and using a fourth mask, forming a pixel electrode such that the pixel electrode is electrically connected to the source and drain electrodes, the gate pad, and the data pad.

Further, an embodiment of an array substrate for an active matrix type liquid crystal display device includes a substrate; a gate line above on substrate; a gate pad at one end of the gate line such that a gate pad contact hole is formed to expose the substrate; a first insulating layer on the gate line; a data line over the first insulating layer to form a crossing point between the gate and data lines and the data line extending into a direction of the gate line to form a source electrode, and wherein a data pad is formed at one end of the data line; a drain electrode formed space apart from the source electrode over the gate line, the drain electrode also extending into a rectangular region defined by the gate and data lines; and a pixel electrode formed over the structure to be electrically connected to the source and drain electrodes, gate pad, and data pad, and wherein the pixel electrode is extended over a portion of the gate line as a capacitor electrode of a storage capacitor such that the storage capacitor includes the portion of the gate line, the extended portion of the pixel electrode, and the first insulating layer disposed inbetween.

The foregoing and other objectives of the present invention will become more apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which like reference numerals denote like parts, and in which:

FIG. 1 is a schematic cross-sectional view of a conventional LCD device;

FIG. 2 is a plan view illustrating a portion of an array substrate of the conventional LCD device;

FIGS. 3A to 7A illustrate a cross-sectional view of conventional sequential fabricating steps along the line “IIIa—IIIa” of FIG. 2;

FIGS. 3B to 7B are illustrate a cross-sectional view of corresponding conventional sequential fabricating steps along the line “IIIb—IIIb” of FIG. 2;

FIG. 8 is a block diagram illustrating the sequence of the conventional fabricating steps of the array substrate;

FIG. 9 is a plan view illustrating an array substrate according to a preferred embodiment of the present invention;

FIGS. 10A to 10D illustrate a sequence of cross-sectional views taken along a line “X—X” of FIG. 9, corresponding to the sequence of fabricating steps according to the invention;

FIG. 11 is a cross-sectional view taken along the line “XI—XI” of FIG. 9; and

FIG. 12 is a cross-sectional view taken along the line “XII—XII” of FIG. 9.

DETAILED DESCRIPTION OF PREFFERED EMBODIMENTS

Referring now to the drawings, and more particularly to FIG. 9, an array substrate according to a preferred embodiment of the present invention is described.

A gate line 102, including a gate pad 106 at one end, is arranged in one direction, and a data line 120, including a data pad 126 at one end, is arranged perpendicular to the gate line 102. Gate and data pad electrodes 107 and 109 are positioned over the gate and data pads 106 and 126, respectively. Pixel electrode 118 is positioned in the rectangular area defined by the gate and data lines 102 and 120.

Over the gate and data pads 106 and 126, a gate electrode contact hole 108 and a data electrode contact hole 128 are positioned, respectively. The gate pad electrode 107 is electrically connected with the gate pad 106 via the gate pad contact hole 108, and the data pad electrode 109 is electrically connected with the data pad 126 via the data pad contact hole 128.

Near the crossing point between the gate and data lines 102 and 120, a source electrode 112 is protruded from the data line 120. Spaced apart from the source electrode 112, a drain electrode 114 is positioned. Overlapped by the source and drain electrodes 112 and 114, a portion of the gate line 102 is used as a gate electrode 101. The gate, source, and drain electrodes 101, 112, and 114 make up a thin film transistor (TFT) 110.

Over the drain electrode 114, a drain contact hole 116 is positioned. The pixel electrode 118 is electrically connected with the drain electrode 114 via the drain contact hole 116.

Spaced apart from the drain electrode 114, a portion of the pixel electrode 118 is extended to form a capacitor electrode 150. The capacitor electrode 150 overlaps a portion of the gate line 102. Between the capacitor electrode 150 and the gate line 102, a short-preventing portion 160 is positioned to prevent short circuits from occurring therebetween. The capacitor electrode 150 and the overlapped portion of the gate line 102 make up a storage capacitor 140.

Further, a passivation layer 122 covers the data line 120, and the source and drain electrodes 112 and 114.

Hereinafter, with references to FIGS. 10A to 10D, the fabricating process of the array substrate according to a preferred embodiment of the present invention will be explained in detail.

As shown in FIG. 10A, on a surface of a substrate 1, a first metallic material and a first insulating material are deposited sequentially, and both are patterned with a first mask to form the gate line 102 and a first insulating layer 200. A portion of the gate line 102 is used as the gate electrode 101. The first metallic material can include molybdenum (Mo), Chromium (Cr), and/or aluminum-neodymium-molybdenum alloy.

Further, at one end of the gate line 102, the gate pad contact hole 108 is formed in the gate pad 106, thereby defining a fourth intermediate structure. The gate pad contact hole 108 makes possible interconnection between the gate pad 106 and the pixel electrode 118 (shown in FIG. 10d). Multiple smaller gate pad contact holes (not depicted) are preferred over one equivalently large gate pad contact hole, to decrease the contact resistance between the pixel electrode 118 and the gate pad 106.

Next, as shown in FIG. 10B, on the fourth intermediate structure, a second insulating material, a semiconductor material, a doped semiconductor material, and a second metallic material are deposited sequentially to form the second insulating layer 202, the semiconductor layer 204, the ohmic contact layer 206, and the second metal layer. The second metal layer is patterned with a second mask so as to form the source and drain electrodes 112 and 114, the data line 120.

Afterwards, the ohmic contact layer 206 is etched, using the second patterned metal layer as a mask, to form a back channel 208 and decrease leakage current, thereby defining a fifth intermediate structure. Also, the second insulating layer 202 prevents short circuits at a stepped portion “T” between the gate line 102 and the data line 120.

Next, as shown in FIG. 10C, over the surface of the fifth intermediate structure, a third insulating material is deposited and patterned with a third mask to form the passivation layer 122. When patterned with the third mask, the overall portions of the ohmic contact layer 206, the semiconductor layer 204, and the second insulating 202, except for portions under the third mask, are etched away, thereby defining a sixth intermediate structure. At this point, the first insulating layer 200 remains and protects the gate line 102 and the gate pad 106. The third mask covers the patterned second metal layer and a peripheral portion of the gate line 102, which will be overlapped with a pixel electrode 118 (see FIG. 11). The passivation layer 122 also includes the data pad contact hole 128 (see FIG. 12).

Finally, as shown in FIG. 10D, over the surface of the sixth intermediate structure, a transparent conductive material is deposited and patterned with a fourth mask to form the pixel electrode 118. At this point, over the gate pad 106, the gate pad electrode 107 contacting the gate pad 106 via the gate pad contact hole 108 is also formed of the same material. The transparent conductive material is preferably indium tin oxide (ITO) or indium zinc oxide (IZO).

Now, referring to FIG. 11, the structure of the storage capacitor 140 (shown in FIG. 9) will be explained. After the passivation layer 122 is formed using the third mask, portions of the ohmic contact layer 206, the semiconductor layer 204, and the second insulating 202 over the gate line are etched away except for the short-preventing region 160. As mentioned above, the first insulating layer 200 remains to protect the gate line 102.

Then, after the transparent conductive material is deposited and patterned with the fourth mask, the capacitor electrode 150 is formed. The capacitor electrode 150 extends from the pixel electrode 118 and overlaps a portion of the gate line 102. The first insulating layer 200 is interposed therebetween. The capacitor electrode 150 and the overlapped portion of the gate line 102 and the first insulating layer 200 interposed therebetween make up the storage capacitor 140.

The short-preventing portion 160 is positioned at the stepped portion “Z” between the stepped end of the gate line 102 and the step of the capacitor electrode 150 to prevent short circuits from occurring between the capacitor electrode 150 and the gate line 102. Portions 122 a, 202 a, 204 a and 206 a of the passivation layer, the second insulating layer, the semiconductor layer, and the ohmic contact layer 122, 202, 204, and 206 make up the short-preventing portion 160.

Referring to FIG. 12, the structure of the data pad according to the preferred embodiment of the present invention will be explained. After the second metal layer is patterned with a second mask, the data pad 126 is formed in addition to the source electrode 112, the drain electrode 114, and the data line 120. Also, the semiconductor layer 204 and the ohmic contact layer 206 are formed. Afterwards, when the passivation layer 122 is formed using the third mask, the data pad contact hole 128 is also formed.

Then, after the transparent conductive material is deposited and patterned with the fourth mask, the data pad electrode 109 is formed. The data pad electrode 109 is made of the same material as the pixel electrode 118 (shown in FIGS. 9 and 11), and covers the passivation layer 122 and the data pad 126. The data pad contact hole 128 interconnects the data pad 126 and the data pad electrode 109.

As described above, the fabricating method according to the preferred embodiment of the present invention employs only four masks, and therefore provides a less expensive and more reliable method of manufacturing an active-matrix LCD device.

While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention. 

What is claimed is:
 1. A method of fabricating an array substrate for an active matrix type liquid crystal display (LCD) device, the method comprising: a) preparing a substrate; b) forming a plurality of gate lines, a plurality of gate pads and gate pad contact holes, and a first insulating layer by depositing a first metal layer and depositing a first insulating layer sequentially on a surface of the substrate and patterning the first metal layer and the first insulating layer to have substantially the same pattern with a first mask such that the plurality of gate lines are parallel with and spaced apart from each other wherein each gate pad is positioned at one end of a corresponding gate line, and wherein each gate pad contact hole has a shape of a through hole passing through the gate pad and the first insulating layer; c) forming a second insulating layer, a semiconductor layer, an ohmic contact layer, and a second metal layer by depositing a second insulating material, a semiconductor material, a doped semiconductor layer, and a second metallic material sequentially over the surface of the substrate; d) forming a plurality of data lines, data pads, source electrodes, drain electrodes, and drain contact holes by patterning the second metal layer with a second mask wherein the data lines cross the gate lines, each data pad is positioned at one end of a corresponding data line, each source electrode is extended from the data lines near the crossing point of the gate line and the data line, the drain electrode is spaced apart from the source electrode, and wherein the drain contact hole is positioned on the drain electrode; e) forming a plurality of back-channels by etching away portions of the ohmic contact layer using the patterned second metal layer as a mask, wherein the channel is positioned between the source and the drain electrodes; f) depositing a third insulating layer on the data lines, the source and the drain electrodes, and the data pads; g) patterning the third insulating layer, the ohmic contact layer, the semiconductor layer and second insulating layer with a third mask to form a passivation layer, wherein the passivation layer has a data pad contact hole having a shape of a through hole positioned over the data pad, and wherein the passivation layer contacts a portion of the second insulating layer and covers the patterned second metal layer and a peripheral portion of the gate line; and h) forming a plurality of pixel electrodes, data pad electrodes, and gate pad electrodes by depositing a transparent conductive layer on the passivation layer, and patterning the transparent conductive layer by a fourth mask, wherein a portion of the pixel electrode overlaps the peripheral portion of the gate line, the pixel electrode is electrically connected with the drain electrode via the drain contact hole, the data pad electrode is electrically connected with the data pad by way of the data pad contact hole, and wherein the gate pad electrode is electrically connected with the gate pad via the gate pad contact hole.
 2. The method according to claim 1, wherein the each gate pad contact hole includes at least one through hole.
 3. The method according to claim 1, wherein the peripheral portions of gate lines having portions of the second insulating layer, the semiconductor layer, the ohmic contact layer, and the passivation layer are used for preventing short-circuits between the gate line and the data line.
 4. The method according to claim 1, wherein the transparent conductive layer is selected from a group consisting of indium tin oxide and indium zinc oxide.
 5. The method according to claim 1, wherein the semiconductor layer is an amorphous silicon layer.
 6. A method of fabricating an array substrate for an active matrix type liquid crystal display (LCD) device, said method comprising: a) depositing a first conducting material and depositing a first insulating material on top of said first conducting material on a substrate; b) using a first mask, forming a gate line, a gate pad at one end said gate line, a first insulating layer over said gate line and gate pad, and at least one gate pad contact hole in said gate pad, the first insulating layer, gate pad and gate line having substantially the same pattern; c) depositing, in sequence, a second insulating layer, a semiconductor layer, an ohmic contact layer, and a second conducting material over the structure resulting from said step b); d) using a second mask to pattern said second conducting material, forming a data line such that said data line crosses said gate line and forming source and drain electrodes at said crossing point; e) forming a back channel between said source and drain electrodes by etching said ohmic contact layer using said source and drain electrodes as a mask; f) forming a passivation layer by depositing a third insulating layer over the structure resulting from said step d), wherein said passivation layer contacts a portion of the second insulating layer; g) using a third mask, removing said second insulating layer, said semi conductor layer, said ohmic contact layer, and said passivation layer over a portion of said gate line and said gate pad; h) depositing a transparent conductive material over the structure resulting from said step g); and i) using a fourth mask, forming a pixel electrode such that said pixel electrode is electrically connected to said source and drain electrodes, said gate pad, and said data pad.
 7. The method of claim 6, wherein said first conducting material is selected from at least one of molybdenum (Mo), chromium (Cr), and aluminum-neodymium-molybdenum alloy.
 8. The method of claim 6, wherein step b), a surface of said substrate is exposed due to said gate pad contact hole.
 9. The method of claim 6, wherein said second conducting material is selected from at least one of molybdenum (Mo), chromium (Cr), and aluminum-neodymium-molybdenum alloy.
 10. The method of claim 6, wherein in step d), said source electrode is formed by extending a portion of said data line in a direction of said gate line.
 11. The method of claim 6, wherein said drain electrode extends into a rectangular region defined by said gate and data lines.
 12. The method of claim 6, wherein in step g), said surface of said substrate is exposed again due to said gate pad contact hole.
 13. The method of claim 6, wherein said transparent conductive material is selected from one of indium tin oxide (ITO) and indium zinc oxide (IZO).
 14. The method of claim 6, wherein said pixel electrode is extended over a portion of said gate line to form a capacitor electrode of a storage capacitor wherein said storage capacitor includes said portion of said gate line, said extended portion of said pixel electrode, and said first insulating layer disposed inbetween.
 15. The method of claim 14, wherein a short preventing part is formed between an edge of said gate line and said pixel electrode.
 16. The method of claim 15, wherein said short preventing part includes portions of said second insulating layer, said semiconductor layer, said ohmic contact layer, and said passivation layer. 